1. Field of the Invention
This disclosure relates to a semiconductor device and a method of manufacturing the same. More particularly, the disclosure relates to a semiconductor device capable of preventing the “punchthrough” phenomenon between source and drain regions of a transistor, improving the refresh characteristics of a memory cell, and a method of manufacturing the same.
2. Description of the Related Art
FIG. 1 is a cross-sectional view of a conventional MOS transistor. Referring to FIG. 1, the MOS transistor comprises a gate electrode 3 stacked on a semiconductor substrate 1 with a gate oxide layer 2 interposed between them, with source regions 4 and drain region 5 formed on the surface portions of the substrate 1 adjacent to either side of the gate electrode 3.
Carriers such as electrons or holes are supplied at the source region 4 and are removed at the drain region 5. The gate electrode 3 plays the role of forming a surface inversion layer, i.e., a channel, extending between the source region 4 and the drain region 5.
When scaling down the MOS transistor as the integration level of semiconductor devices increases, the reduction in the length of the gate electrode is far more dramatic than the reduction of the operating voltage. With the down scaling of the gate length, the influence of the source/drain upon the electric field or the potential in the channel region of the MOS transistor is considerable. This influence is known as the “short channel effect” and a lowering of the threshold voltage is a typical result of this phenomenon. This is because the channel region is greatly influenced by the depletion charge, the electric field, and the potential distribution of the source/drain regions as well as the gate electrode.
In addition to a decreased threshold voltage, punchthrough between the source and drain regions is another severe problem accompanying the short channel effect.
In the MOS transistor of FIG. 1, the drain depletion layer 7 is widened in proportion to the increase in the drain voltage, so that the drain depletion layer 7 comes close to the source region 4. Thus, the drain depletion layer 7 and the source depletion layer 6 are completely connected to each other when the length of the gate electrode 3 is decreased. The electric field of the drain may eventually penetrate into the source region 4 and thereby reduce the potential energy barrier of the source junction. When this occurs, an increased number of major carriers in the source region 4 possess sufficient energy to overcome the barrier. Thus, a larger current flows from the source region 4 to the drain region 5. This effect is called the “punchthrough” phenomenon. When punchthrough occurs, the drain current is not saturated but rapidly increases towards the saturation region.
In general MOS transistor technology, a threshold voltage (Vt) adjustment is performed in order to secure the desired threshold voltage. The threshold adjustment is an implant process. For example, a p-type impurity such as boron (B) is ion-implanted in the NMOS transistor.
When the drain voltage is relatively small in the short-channel MOS transistor, the drain depletion layer is not directly in contact with the source region. However, the surface of the substrate is depleted to some degree by the gate electrode, thereby varying the height of the potential barrier near the source. This is known as “surface punchthrough”. The threshold adjustment process increases the doping concentration of the interface between the substrate and the gate oxide layer, thereby suppressing surface punchthrough as well as adjusting the threshold voltage.
Accordingly, as down scaling of the gate length progresses, the threshold adjustment process is performed at a high doping concentration to suppress the punchthrough. Typically, the source and drain regions make contact with the heavily-doped threshold adjustment region because the impurities are applied to the entire surface of the substrate. Thus, in the NMOS transistor, the n-type source and drain regions make contact with the p+ region (i.e., threshold adjustment region) to apply the high electric field on the p-n junction, thereby increasing the junction leakage current.
In dynamic random access memory (DRAM) devices, in which a unit memory cell consists of one transistor and one capacitor cell, a “refresh” operation (i.e., a data restoring operation for recharging the data charge) is necessary because the data charge of the capacitor decreases due to the leakage current over time. Typically, the cell transistor is an NMOS transistor. Therefore, the junction leakage current increases due to the high electric field at the p-n junction where the n-type source/drain makes contact with the p+ region (i.e., the threshold adjustment region) when a high dose threshold adjustment implantation is performed. This results in the deterioration of the refresh operation.
U.S. Pat. No. 5,963,811 discloses a method of forming a heavily doped anti-punchthrough region in the interface between the source and drain regions and the cell region through an additional ion-implantation process after the threshold adjustment is performed. Methods of locally forming an anti-punchthrough region directly below the gate electrode are disclosed in U.S. Pat. Nos. 5,484,743; 5,489,543; and 6,285,061.
However, in these methods, the anti-punchthrough region extends to the source and drain regions due to the profile of the lateral projection range (Rp) caused by the ion-implantation. Accordingly, a large electric field is applied to the region where the n-type source and drain regions and the p-type channel region make contact with each other, generating an increased junction leakage current and a deterioration of the refresh operation.
Furthermore, Japanese Patent Laid Open Publication No. 9-045904 discloses a method of forming a partition for preventing punchthrough below the channel region. The partition is formed of an insulator or alternatively formed by filling the interior of the insulator with a conductor. In the case of using a partition comprised of an insulator, the current path of the depletion layer penetrates to the source side when the drain depletion layer meets the partition, thereby generating punchthrough. The method of forming the partition by filling the interior of the insulator with a conductor can prevent this problem, but the required manufacturing process is complicated.